1. Field of the Invention
This invention relates to semiconductor devices and processes, and in particular to dielectrically isolated planarized SOS semiconductor devices and processes for constructing such devices.
2. Description of the Prior Art
With the advent of complementary metal-oxide-silicon devices (CMOS), it became clear that the construction of such devices on a bulk silicon substrate was undesirable since the P-channel and N-channel devices were electrically connected through the common silicon substrate. Construction of CMOS devices on a sapphire substrate, commonly referred to as silicon-on-sapphire (SOS), produces the desirable result of dielectrically isolating the P-channel and N-channel devices by means of the sapphire substrate. As a result of constructing the devices on a sapphire substrate, additional difficulties which affected yield have been encountered.
FIG. 1 is a schematic illustration of a CMOS device on a sapphire substrate as constructed using prior art processing. Silicon islands 50 with source regions 52, drain regions 54, and gate regions 55 are physically separated on a sapphire substrate 56. FIG. 2 is a cross-section through the line II-II of a portion of one of the silicon islands 50 through the gate region 55. A thin layer of silicon dioxide forms a gate oxide 58 which is sandwiched between silicon island 50 and the metal electrode 60. The gate oxide 58 and metal electrode 60 both extend over the step or corner 62 of the silicon island 50. While metal electrode 60 extends to the surface 64 of the sapphire substrate 56, the gate oxide 58 is typically incomplete at the surface 64 of the sapphire substrate 56 because of incomplete growth during oxidation. This incomplete growth frequently results in a small gap 66 in the gate oxide 58 at the surface 64 of the sapphire substrate 56 into which some metal from the metal electrode 60 may be deposited. This gap 66 results in a weak area in the gate oxide 58 through which an oxide breakdown resulting in a short circuit of the metal electrode 60 to the silicon island 50 frequently occurs. Furthermore, oxide breakdown at the step or corner 62 of the silicon island 50 is also enhanced because of high electric fields generated at the corner 62.
Construction of the device as illustrated in FIGS. 1 and 2 also results in additional difficulties in subsequent masking steps when it is necessary to focus on the surface of the silicon island 50 and the surface of the sapphire substrate 56. Because of depth of field limitations due to the height of the silicon island 50 above the surface of the sapphire substrate 56, it is difficult to focus the mask on both surfaces simultaneously, thereby resulting in resolution problems and possible distortion of desired shapes, and in particular, causing metalization shorts.
In the processing of complementary P-channel and N-channel devices or MOS transistors, it is desirable that the distance between the respective gate regions be as consistent as possible because the processing steps for forming the gate oxides are usually performed with a single mask. In the prior art, misregistration between the two gate regions frequently occurred, thereby resulting in excessive gate metal over the source or drain regions, which increases the overlap capacitance and decreases the speed at which the device may operate.
Radiation induced charge in the sapphire substrate significantly affects operation of the N-channel device. In a radiation environment, the sapphire acquires a positive charge which is located near the sapphire-silicon interface. The positive charge in the sapphire attracts a negative charge to the interface in the silicon, thereby creating a back channel for electron flow which is not controlled by the normal top surface gate. In the prior art, this back-channel leakage effect frequently occurs, thereby detrimentally affecting the operation of the N-channel device.
Critical in the construction of an MOS device is the overlap of the gate oxide over the source and drain regions. The prior art requires an oversized gate window to compensate for misalignment so as to assure that the thin gate region overlaps both the source and drain regions. This overlap results in a higher overlap capacitance, thereby decreasing the speed at which the device may operate.
It is therefore desirable to construct silicon islands on a sapphire substrate with devices therein which may be interconnected without traversing steps, corners and gaps at the silicon island edges.
It is desirable to have the surface of the silicon islands and the surfaces in between the silicon islands at the same height above the sapphire substrate to eliminate depth of field variations during masking steps.
It is desirable to prevent device gate metal from overlapping the source and drain regions which increases the gate capacitance due to misregistration between two device regions of different types or due to mask misalignment with one device region.
It is desirable to prevent back channel leakage in an N-channel device after charge has been induced in the supporting sapphire substrate due to ionizing radiation.